From 7026db1a9d4a74583241a2ac8e37db9139432e77 Mon Sep 17 00:00:00 2001 From: Debian Qt/KDE Maintainers Date: Thu, 16 Apr 2020 18:05:12 +0100 Subject: [PATCH] add RISC-V detection Origin: upstream, https://code.qt.io/cgit/qt/qtbase.git/commit/?id=9a6a84731131b205 Last-Update: 2019-12-31 Gbp-Pq: Name riscv.diff --- src/corelib/global/archdetect.cpp | 4 +++ src/corelib/global/qglobal.cpp | 36 ++++++++++++++++++++++++ src/corelib/global/qprocessordetection.h | 14 +++++++++ 3 files changed, 54 insertions(+) diff --git a/src/corelib/global/archdetect.cpp b/src/corelib/global/archdetect.cpp index 66a5e074f..1d00b7f5a 100644 --- a/src/corelib/global/archdetect.cpp +++ b/src/corelib/global/archdetect.cpp @@ -67,6 +67,10 @@ # define ARCH_PROCESSOR "power" #elif defined(Q_PROCESSOR_POWER_64) # define ARCH_PROCESSOR "power64" +#elif defined(Q_PROCESSOR_RISCV_32) +# define ARCH_PROCESSOR "riscv32" +#elif defined(Q_PROCESSOR_RISCV_64) +# define ARCH_PROCESSOR "riscv64" #elif defined(Q_PROCESSOR_S390_X) # define ARCH_PROCESSOR "s390x" #elif defined(Q_PROCESSOR_S390) diff --git a/src/corelib/global/qglobal.cpp b/src/corelib/global/qglobal.cpp index 01f534cc0..41dcbbaab 100644 --- a/src/corelib/global/qglobal.cpp +++ b/src/corelib/global/qglobal.cpp @@ -1870,6 +1870,42 @@ bool qSharedBuild() Q_DECL_NOTHROW \sa QSysInfo::buildCpuArchitecture() */ +/*! + \macro Q_PROCESSOR_RISCV + \relates + \since 5.13 + + Defined if the application is compiled for RISC-V processors. Qt currently + supports two RISC-V variants: \l Q_PROCESSOR_RISCV_32 and \l + Q_PROCESSOR_RISCV_64. + + \sa QSysInfo::buildCpuArchitecture() +*/ + +/*! + \macro Q_PROCESSOR_RISCV_32 + \relates + \since 5.13 + + Defined if the application is compiled for 32-bit RISC-V processors. The \l + Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_32 is + defined. + + \sa QSysInfo::buildCpuArchitecture() +*/ + +/*! + \macro Q_PROCESSOR_RISCV_64 + \relates + \since 5.13 + + Defined if the application is compiled for 64-bit RISC-V processors. The \l + Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_64 is + defined. + + \sa QSysInfo::buildCpuArchitecture() +*/ + /*! \macro Q_PROCESSOR_S390 \relates diff --git a/src/corelib/global/qprocessordetection.h b/src/corelib/global/qprocessordetection.h index 77b3ba36b..7ff711b5c 100644 --- a/src/corelib/global/qprocessordetection.h +++ b/src/corelib/global/qprocessordetection.h @@ -281,6 +281,20 @@ # endif // Q_BYTE_ORDER not defined, use endianness auto-detection +/* + RISC-V family, known variants: 32- and 64-bit + + RISC-V is little-endian. +*/ +#elif defined(__riscv) +# define Q_PROCESSOR_RISCV +# if __riscv_xlen == 64 +# define Q_PROCESSOR_RISCV_64 +# else +# define Q_PROCESSOR_RISCV_32 +# endif +# define Q_BYTE_ORDER Q_LITTLE_ENDIAN + /* S390 family, known variant: S390X (64-bit) -- 2.30.2